), resetting it to zero
), and "jumping" to a new state
). Rather than encode the next-state function as actual state bits, you can implement it by asserting the counter control signals CNT, LD, and CLR under the right conditions. We examine a counter-based implementation strategy in this section.
For correct operation in state sequencing, the counter must be implemented with synchronous LD and CLR signals, such as the TTL 74163 binary up-counter. As pointed out in Section 7.5.2, asynchronous control signals lead to invalid behavior of the state machine.
)to a state
(other than 0
)takes place. The figure shows three such jumps: from state 0 to 4, from 1 to 5, and from 5 to 3.
), as well as the counter load inputs C, B, and A. Our basic procedure obtains minimized logic expressions for these signals rather than the next-state bits.
For the 74163 counter, the signal has precedence over , which in turn has precedence over EN
). This makes it possible to exploit many more don't-care conditions within the K-maps.
We derive the state transition table in the following manner. We examine each state transition in turn. Consider the first transition, from state 0 to 1. If the machine is currently in state 0 with input 0, the finite state -machine changes to state 1 with output 1. Thus, and should be unasserted
)and EN asserted to cause the state register to count up from 0 to 1. These settings fill out the rest of the row in the transition table.
Boolean Minimization of the Counter Control Signals Our next step is to minimize the functions for Z, , , and EN. The espresso input file is shown in Figure 10.22 and the resulting output file in Figure 10.23.
Because we are already using the signal for a control function, we need a separate RESET input to place the finite state machine in state 0 initially. Note that this is a synchronous reset; the reset on the 74175 quad registers used in some of the finite state machine implementations in this chapter is asynchronous. To be correctly "synchronous," we should include a reset signal as input to the ROM or PLA/PAL next-state logic
(see Exercise 10.2
The counter-based implementation was a bad choice for this particular state machine. However, when the state diagram has fewer out-of-sequence jumps, a counter-based implementation can be very effective