Saturday, 5 October 2013

Digital Components

2.1. Integrated Circuits

2.1.1. ICs

2.1.1. SSI, MSI, LSI, VLSI

SSI: Small-scale integration, a few gates per chip. Example: TTL 7400 series.
MSI: Medium-scale integration, a dozens or hundreds of gates per chip.
LSI: Large-scale integration, up to several thousand gates per chip.
VLSI: Very large-scale integration, many thousands or millions of gates per chip. ( Modern microprocessors. )

2.1.2. TTL, ECL, MOS, CMOS

2.2. Encoders and Decoders

2.2.1. Decoders

A decoder converts an n-bit unsigned binary number to a '1' on exactly one of 2n outputs.
An optional enable input, if 0, causes all outputs to be 0.

2.2.2. Encoders

An encoder outputs an n-bit unsigned binary number that identifies which of the 2n inputs is '1'.
If more than one input is one, the output is undefined. ( It is predictable if the gate-level design of the encoder is known, but the definition of an encoder requires that only one input be 1. )

2.3. Multiplexers and Demultiplexers

2.3.1. Multiplexers

A multiplexer routes one of 2n inputs to the single output line. The input is selected by the select inputs, which are interpreted as an n-bit unsigned binary number.

2.3.2. Demultiplexers

A demultiplexer routes a single input to one of 2n output lines. The output line is selected by the select inputs, which are interpreted as an n-bit unsigned binary number.
Note that a demultiplexer is exactly the same circuit as a decoder with an enable input. The enable input on a decoder can be viewed as the data input of a demultiplexer which is routed to one of the outputs.

2.4. Registers

A register is a sequence of flip-flops used to store a word of binary information. A word is any number of bits of data, and is defined by the architecture of the CPU. For example, a 64-bit CPU such as an AMD Sempron uses a 64-bit word. An 8-bit CPU such as a Z80 uses an 8-bit word.

2.4.1. Parallel Load

A parallel load input, when '1', causes the data on the inputs of the register to be loaded into the register upon the next clock trigger. Where does the register load in the timing diagram below if the register is leading-edge triggered? If it's trailing-edge triggered? If it's high-level triggered?
	CK  _-_-_-_-_-_-_-_-_-_-_-_-_
	LD  ______________-------____
Implement parallel load register with D flip-flops and extra gates.

2.4.2. Clear

2.4.3. Complement

Multiple functions may be encoded to reduce the number of control wires on the register. For example, 3 control wires could select one of 8 operations. ( 000 = load, 001 = clear, 010 = complement, ... )

2.5. Shift Registers

A shift register is capable of moving the contents of each flip-flop to a neighboring flip flop. Shift operations are usually called left shift and right shift.
Bits vacated by a shift (e.g. the rightmost bit in a left shift) are filled by one of several methods:
  • Set to 0 (logical shift)
  • Left unchanged. Used for right-shift only, this is an arithmetic shift. It has the effect of dividing a two's complement integer by 2, regardless of sign.
  • Brought in from outside the register. This is used in serial communication. Data coming over the communication wire is brought into the outermost bit of the register at each clock pulse. After n shifts, an n-bit word has been loaded in serial fashion. Some common simple serial communication systems are X2C and SPI.
Likewise, the bits shifted out of the register have more than one possible destiny. They may be
  • Lost.
  • Stored in the CPU's status register as an indicator.
  • Shipped out over a serial communication line as input to the receiving shift register. 

2.6. Binary Counters

A binary counter is a register with the ability to increment itself. The internal logic for making this happen is relatively simple, but is left to a course in digital logic. Binary counters are commonly used as timers. By knowing the clock frequency and reading the value of a counter that has been continuously enabled, one can determine how much real time has passed. Given the clock speeds are very high on modern processors (MHz or GHz), small counters (16 or even 32 bits) will overflow (go from all 1's to all 0's) after a short time. This even can often be configured to generate an interrupt, so that software can count the overflows and thus extend the range of the timer.

2.7. Memory Unit

2.7.1. RAM (Random Access Memory)

Bad name. ROM is also randomly accessible. RAM refers to read/write memory, and probably should be called RWM.
RAM is also known as volatile memory, since its contents disappear (evaporate) when power is cut.
  • k address lines for 2k memory cells. (Usually one byte each.)
  • n input data lines (n usually = 8)
  • n output data lines (n usually = 8)
  • Read/Write select Static RAM Dynamic RAM

2.7.2. ROM ROM

Combinational circuit! ( Outputs depend only on inputs, i.e. address. ) Can be used to implement combinational functions without building a custom circuit. Contents set at the factory. Unlike RAM, retains contents when power is off. Hence, ROM is also known as nonvolatile memory. PROM

Comes from the factory with all 1's or all 0's. Programmed by blowing fuses at desired bit positions to change from 1 to 0 or 0 to 1. EPROM

Electronically programmable ROM: Can be programmed without highly specialized equipment, and can be erased using ultraviolet light and then reprogrammed. Uses fuses that are not destroyed in the programming process. EEPROM

Electronically erasable programmable ROM. Can be erased using normal input signals - no need for UV. FLASH RAM is technically in this category of memory, although it is much more versatile than original EEPROMs. FLASH RAM is usually limited to something on the order of 100,000 write cycles. ( Problem for FLASH hard disks. )

2.8. Circuit Implementation

2.8.1. ASICs (Application-Specific Integrated Circuits)

2.8.2. PLAs (Programmable Logic Arrays)

2.8.3. FPGAs (Field-Programmable Gate Arrays)

FPGAs can be programmed to simulate any combinational circuit, as well as many sequential circuits. They have some advantages over ASICs:
  • Can be programmed in-house, whereas ASICs usually need to be fabricated in a specialized factory, which is expensive and may cause delays.
  • FPGAs protect intellectual property. Your circuit design never has to be given to another company in order to implement the circuit. FPGAs are very difficult to reverse-engineer. (It's hard to determine the complete functionality of the FPGA when it implements a complex circuit.)
  • When bugs are discovered in the circuit design, they can be fixed by reprogramming, rather than replacement of the hardware. 

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