5.6.1 Theory of OperationIn the last section, we saw how to express an 8-bit product as a series of sums of 1-bit products, so-called partial product accumulation. We can exploit the same principle to construct multipliers of wider bit widths using primitive 4-by-4 multiplier blocks.
(See Appendix A to review base conversions.
5.6.2 ImplementationThe basic blocks of the implementation are
)the calculation of partial products,
)the summing of the 4-bit product slices, and
)the carry look-ahead unit. We examine each of these in turn.
Calculation of Partial Products Each of the 8-bit partial products is implemented by a 74284/74285 pair. The subsystem has 16 inputs, the multiplicand and multiplier, and 32 outputs, constituting the four 8-bit partial products. The partial product subsystem is shown in Figure 5.31.
(Watch that you don't confuse the variable Ci with adder carry-ins.
)The first level of full adders sums 1 bit from each of the three numbers to be added. We accomplish this by using the carry input as a data input. The second-level adders combine the carry-out from the next lower order stage with the sum from the first-level adder. The carries simply propagate from right to left among the second-level adders. This is just like the carry propagations we needed in the 4-by-4 multiplier of Figure 5.28.
Putting the Pieces Together The last step in the design combines the multiplier block with the accumulation block. To further improve the performance, the carries between the 74181s can be replaced with a 74182 carry look-ahead unit.
Package Count and Performance In terms of package count, the complete implementation uses four 74284/74285 multipliers
), four 74183 full adder packages, three 74181 arithmetic logic units, and one 74182 carry look-ahead unit. This is a total of 16 packages.
A circuit this complex is far too complicated to analyze by simply counting gate delays. We start by identifying the critical delay path. This is the sequence of propagated signals that limits the performance of the circuit. Once we have determined the critical path, the TTL catalog will provide us with signal delays associated with the individual packages in our implementation.
The first step in the critical path is the calculation of the partial products by the 74284/285 multipliers. Assuming standard TTL components, the typical delay from the arrival of the inputs to valid outputs is 40 ns
(60 ns maximum
The next step in the critical path is the formation of the intermediate sums by the 74183s. We assume LS TTL for these packages. Since the typical adder delay is sensitive to the final value of the sum output, 9 ns for a low-to-high transition and 20 ns for a high-to-low output transition, it is reasonable to average these to get 15 ns. For worst-case delay, we should use the worst-case maximum, which is 33 ns.
The final leg of the critical path is the calculation of the second-stage sums using the carry look-aheads. This consists of three pieces:
)calculation of the group propagates/generates in the 74181s,
)calculations of the carry-outs by the 74182 after the propagates and generates become valid, and
)calculation of the final sums in the 74181s once the carries are valid.
We assume LS TTL for the 74181 and standard TTL for the 74182. For the 74LS181, from inputs valid to group propagate/generate valid takes 20 ns typical
(30 ns maximum
). In this case, the propagate is slightly slower than the generate, so this is the signal that really determines the delay.
Using a standard TTL 74182, the delay from group propagate/generate in to valid carry-outs is 13 ns typical, 22 ns worst case. Returning to the 74LS181, the last piece of the critical path is the delay from carry-in valid to sums valid. This is 15 ns typical, 26 ns worst case.
So the typical delay is 40
)= 103 ns. The worst-case delay is 60 + 33 + 30 + 22 + 26 = 171 ns. There is a significant difference between the worst case and the typical performance. Also, the delay can be significantly reduced by using a faster TTL family, such as S or AS logic.