(labeled count in the figures
). In a fully synchronous counter, the storage elements simultaneously examine their inputs and determine new outputs. This is the preferred way to build counters, but there are other approaches we will examine in this section.
7.5.1 Ripple CountersSome counters avoid the global clock altogether. These elements count by propagating or rippling the decision to change state from one storage element to an adjacent element. Hence these counters are called ripple counters, and we study them next.
Three-Bit Binary Ripple Counter
(the reset logic is not shown
). The lowest-order
(most rapidly changing
)bit is the leftmost. The output from one stage drives the clock of the next stage to the right.
The timing waveform for a typical count sequence is shown in Figure 7.38.
In effect, the ripple counter computes its next state in a serial fashion, rather than in parallel as in the implementation of Figure 7.16. Since the state transitions are not crisp, external logic reading the current state as an input can glitch or "spike" in an undesirable manner. Despite the simpler hardware, you should never be tempted to implement a counter in this fashion.
7.5.2 Synchronous Versus Asynchronous InputsIn Chapter 6 we described some of the dangers in using asynchronous inputs to otherwise synchronous systems. In general, you should try to avoid components with asynchronous inputs.
The ubiquitous 74163 counter illustrates the power of synchronous inputs. In addition to its internal synchronous implementation, it provides synchronous clear and load signals. This makes it ideal for implementing more complex count sequences with a beginning offset or limiting cutoff.
Starting Offset CounterSuppose we need to implement a counter that follows the sequence 0110 through 1111 and then repeats. The RCO signal, in conjunction with a synchronous load input, can implement this function easily.
The logic is shown in Figure 7.41.
This counter is self-starting. Resetting clears the counter to 0000. Although it starts off in an invalid state, it reaches the desired sequence within six clock periods.
The timing waveform is given in Figure 7.42. The signal
(the complement of RCO
)is asserted when the counter enters state 1111. On the next rising clock edge, the counter enters state 0110.
Cutoff Limit CounterSimilarly, we can construct a counter with a cutoff limit by using the synchronous clear signal. For example, we can use the logic of Figure 7.43 to implement a counter that begins at 0000 and sequences through to 1101 before restarting.
If the control inputs were asynchronous, the state change would have happened as soon as the control input was asserted, independent of the clock. This violates a fundamental assumption of synchronous systems-that the state changes at clocking events and not at other times.
Let's reexamine the counter of Figure 7.43, but this time implemented with the TTL 74161 counter. This device is identical to the 74163, except that the clear signal is asynchronous.
Asynchronous inputs should be used only for situations like power-on reset. Never use them to implement state transitions. As a designer, you should always be aware of the behavior of the catalog parts you select. Remember to choose the right parts for the job at hand.