Sunday, 29 September 2013

Techniques used in Hardware Manufacturing

Technology Metrics

When it comes to the performance aspects of the design, there are differences in the underlying technologies that may make one technology more attractive than another. Bipolar circuits come in a wide range of TTL (transistor-transistor logic) families, with different trade-offs in circuit speed and power, and the very high speed ECL (emitter-coupled logic) family. The most popular MOS family is CMOS (complementary MOS), consisting of both n-channel and p-channel devices (see Appendix B).
The main technology metrics, summarized in Figure 2.58, include gate delay, degree of integration, power dissipation, noise margin, component cost, fan-out, and driving capability. In general, faster gates consume more power, generate more heat, cannot be packaged as densely, and are more sensitive to noise problems.

Gate delay: If an input change causes an output change, the gate delay is the time delay between the changes. It is usually measured from the input reaching 90% of its final value to the output reaching 90% of its final value. In general, bipolar technologies are faster than MOS, with ECL achieving the fastest switching times, although the gap between MOS and bipolar is narrowing.
Degree of integration: This represents the area required to implement a given function in the underlying technology. MOS circuits pack much more densely than bipolar. For small-scale integrated (SSI) circuits, a package containing up to 10 logic gates, and for medium-scale integrated (MSI) circuits, a package containing up to 100 gates, this metric is probably not very important. However, in large-scale gate arrays and very large scale integrated circuits (VLSI), containing thousands of gates, MOS has a distinct integration advantage over bipolar.
Power dissipation: Gates consume power as they perform their logic functions, generating heat that must be dissipated. Bipolar circuits typically switch faster than MOS, thus generating more heat and consuming more power. ECL circuits consume the most power. MOS circuits, especially CMOS, can be designed to consume very little power, as evidenced by the lifetime of the battery powering a digital watch's CMOS circuitry. However, in MOS circuits, power is in part a function of the frequency with which the circuit changes outputs. Surprisingly, CMOS circuits may exceed the power dissipation of bipolar circuits at the same very high switching speeds.
Noise margin: This is the maximum voltage that can be added to or subtracted from the logic voltages and still have the circuit interpret the voltage as the correct logic value. Modern TTL and CMOS technologies have good noise margins. ECL gains some of its speed from reduced voltages for representing 0 and 1, and this reduced voltage swing requires tighter noise margins.
Component cost: In general, TTL components are very inexpensive, MOS components are medium in cost, and ECL components are the most expensive.
Fan-out: We defined fan-out in Chapter 1 as the number of gate inputs to which a given gate output could be connected because of electrical limitations. Fan-out is a metric related to the ease with which gates can be composed into more complex functions. MOS circuits can be cascaded with a large number of other MOS circuits without suffering degradation in the transmitted signals. However, signal delays do increase with fan-out. The speed of bipolar circuits does not vary with fan-out, but signal quality is dramatically reduced as the fan-out increases.
Driving capability: Discrete gates, as presented in this chapter, are usually placed with other gates in ready-to-use packages. Driving capability measures the speed of communications between packaged components. In general, MOS circuits have less circuit drive than bipolar circuits, making their package-to-package delay greater. Because of differences in the internal electronics, you must be very careful when mixing bipolar and MOS within the same system. Although MOS circuits can drive many other MOS circuits, they can typically drive only a single bipolar circuit.

TTL Packaged Logic

TTL is a family of packaged logic components that enjoys widespread use in industry. In fact, it is so well known by designers that even libraries for VLSI components, implemented in the radically different MOS technology, provide exactly the same kinds of logic functions from NAND gates to binary adders and beyond. Knowledge of the logic functions available in TTL carries over readily to just about every technology that can be used for digital design. And most students learning hardware design for the first time will work with TTL technology in their introductory hardware laboratories.

In this chapter we've seen the various kinds of simple logic gates. A TTL integrated circuit package typically contains several of these. The Texas Instruments 74-series components provide the standard numbering scheme used by industry. For example, the name for a package containing four 2-input NAND gates is "7400," while a "7404" contains six (hex) inverters.

Small- and Medium-Scale Integration Components containing a handful of primitive gates are called small-scale integration or SSI components. These components typically contain fewer than 10 logic gates in a single package. In Chapter 4 we shall meet medium-scale integration or MSI components. These implement more complex functions than simple two-input gates and typically contain between 10 and 100 logic gates.

In TTL technology, logic gates are available in rectangular dual in-line packages, also known as "dips." Pins that connect internal logic to the outside are placed along the two long edges of the package. A 14-pin package is shown in Figure 2.59, along with a diagram of its internal logic and pin connectivity.
A typical 14-pin package measures approximately 0.75 inch in one dimension and 0.3 inch in the other.

TTL packages come in a variety of pin configurations, from 14-pin packages (7 pins per side) all the way up to 64-pin packages (32 pins per side). In a TTL package, the top edge is usually distinguished by an indentation. The pin immediately to the left of this is labeled #1. You will often find a small bump next to this pin.

The pins are numbered counterclockwise starting with pin #1 at the upper left-hand corner. The pin at the lower left-hand corner (pin #7 in this case) is usually connected to ground (GND), while the pin at the upper right-hand corner (pin #14) is connected to the power supply (VCC). If in doubt, you should always consult the data book for the logic components you are using to verify the numbering scheme. Always make sure you under-stand which pins are to be connected to the power supply.

The figure also shows the pin connectivity for a 14-pin package containing four 2-input NAND gates. Notice how the pins are connected within the package to the gates' inputs and outputs. Usually, related input and output pins are adjacent on the package, but this is not always so. You should always consult the logic family's data book for component pin-out maps.

Subfamilies of TTL TTL is a logic family. This means that the components have been designed so they can be interconnected without too much concern about proper electrical operation. For example, all TTL components operate with a 5 V power supply. There are actually several subfamilies of TTL, all implementing the same logic functions but representing different trade-offs between speed of operation and the amount of power they consume. In general, the faster the component, the more power it consumes.

Standard TTL components are listed as 74XX, where XX is the component number. High-speed TTL components are denoted by 74HXX and low-power TTL components by 74LXX. H components are about one third faster than standard but use twice as much power. L components use one tenth of the power but experience four times the delay. These families were popular in the 1970s but are now considered obsolete.

A major innovation was the introduction of Schottky TTL in the mid-1970s. The internal design of the gates was changed to incorporate a faster kind of transistor structure. The 74SXX family was faster than H TTL but used about the same power as H. This led to the introduction of LS TTL, low-power Schottky TTL, which is one of the most popular families in use today. LS TTL is as fast as standard TTL but uses only 20% of its power.

Innovation did not stop there. Two additional TTL families, AS and ALS are now also available. AS TTL has twice the speed of S TTL at comparable power consumption, and ALS uses less power than LS while offering higher speed. Although the complete catalog of standard components is available in LS TTL, only a relatively small subset is available in these newer technologies.

Speed-Power Product From the preceding discussion, you may find it a little difficult to know which TTL family is best to use. It is always desirable to have a high-speed system, but usually the components are more expensive and the system consumes more power. Higher power consumption translates into a system that runs hotter and needs more expensive cooling and power supplies. An important figure of merit for the purpose of comparing the efficiency of logic families is the speed-power product. To obtain this metric, we multiply the delay through a gate by the power it consumes. Smaller numbers are better: reduced delay and reduced power are ideal.

A typical standard TTL gate has a delay of 9 nanoseconds (ns) and consumes 10 milliwatts (mW). Its speed-power product is 90. The same gate in LS TTL experiences the same delay but consumes only 2 mW. The speed-power product is a better 18. ALS TTL has a delay of 5 ns and consumes only 1.3 mW. Its speed-power product is an even better 6.5. This represents an extremely efficient technology. LS and ALS components are used when the goal is good speed with low power consumption.

Now let's look at higher-speed components. S TTL has a delay of 3 ns, a power consumption of 20 mW, and a speed-power product of 60. Not much faster than ALS, but it uses a lot more power! AS TTL has a delay of 1.6 ns, a power consumption of 20 mW, and a speed-power product of 32. This is the technology of choice for high-speed designs where power consumption need not be low.

So far, we have considered literal count as the primary way to determine the simplicity of a design. Integrated circuit package count is another critical design metric. In TTL technology, a single package typically contains six inverters, four 2-input gates, three 3-input gates, and two complex gates per integrated package.

Look back at the three implementations of the function Z in Figure 2.9. Implementing Z1 in TTL requires three packages: one package of inverters, one package of three 3-input AND gates, and one package of three 3-input OR gates. Z2 also uses three packages: one package of inverters, one package of four 2-input AND gates, one package of four 2-input OR gates. But Z3 needs only two packages. Once again, Z3 is the most area-efficient design.

Schematic Documentation Standards

Although it is frequently ignored, proper documentation is one of the most important skills of a designer. You must be able to describe your design to other designers.

This means that documentation is primarily about standard ways of doing things. It includes the following:
  • Representing the design on paper. This involves ways of drawing components and describing their compositions. A project team must develop and adhere to a standard convention for naming components and the signal wires that interconnect them.
  • Representing interfaces. An interface describes everything you need to know about a subsystem to use it without understanding all its internal workings. This is like the description of a subroutine in a computer program: the documentation describes what the subroutines do as well as the names, types, and functions of its parameters. Hard-ware interfaces are similar to software interfaces, but somewhat more complicated. A hardware interface describes the behavior of the design, as well as the names of signals and how to connect to them.
Standard Schematic Symbols Throughout this chapter, we have used standard gate symbols to represent common SSI components, such as AND, OR, NAND, NOR, XOR, and inverter gates. Gates always have two representations: normal logic and dual logic. The dual representation is used to conserve inversions when using active low signals.
Some examples are shown in Figure 2.60.

These are recognized by digital designers everywhere, so you should use them in your work as well. Do not use any other symbols for the same functions.

Conventions for MSI components are less rigid, but the following are typical. Functions are represented by blocks with input/output signals rather than discrete gates. Figure 2.61 contains a schematic symbol for the 74112 dual J-K flip-flop, a 16-pin TTL component that will be introduced in Chapter 6.

Inputs are drawn on the left, outputs on the right. The general flow of data is from left to right and top to bottom. All signals are labeled with meaningful names. Bubbles on pins or names that end in a slash ("/") indicate signals that are active low. The numbers identify package pin numbers. The connections to ground (pin #8) and the power supply (pin #16) are usually not shown in schematics. Every logic symbol must, without exception, have its part number written inside it.

At times, you will use different instances of the same set of gates in several places in your schematic. The best way to handle this is to draw the gates once, then box them in with a dashed line and label them with a detail letter, as in Figure 2.62.

When you use these gates in a particular place in your schematic, draw a single symbol for the function to be performed, like the single 4-bit wide inverter in the figure, labeling it with the detail letter. The idea is that you expand the detail with its definition.

Names All signals that are not entirely local to an individual schematic drawing must be given a name. If a signal connects to many places in one drawing, it is more convenient to name the signal once and label local wires with this name where it is used, rather than draw wires to connect the uses together.

Names are an important form of documentation, so it is a good idea to name any wire whose usage is not trivial. You should use names that are understandable and describe the function performed by the signal. For example, if a signal causes the B Register to be cleared, then name the signal CLEAR BREG, not 52 or CB. More than one word in a name is fine. Many people capitalize signal names so that they are easy to distinguish from text in documentation. Each signal name must be unique within the project.

Polarization and Bubbles To see an application of practical bubble matching, consider Figure 2.63.

The designer is trying to AND together two related data bits, identified as XA0 and XA1. Unfortunately, the NAND gate output has the opposite sense from what the designer wants: if both bits are 1's, then the NAND output is a 0. As signals pass through levels of logic, it is quite typical for the polarity to switch back and forth.

To make it easier to deal with inverting logic, we think about signals in two separate ways, both of which are reflected in the convention for signal names. The first element of a signal name indicates its function: LOAD PC, or XA<0> AND XA<1>. The second gives the signal's polarity as either high (.H) or low (.L). An .H or .L polarity indicator is added to every signal name to indicate whether its function occurs when the -signal is 1 or 0. For example, in Figure 2.63, the signal XA<0>_AND_XA<1>.L is at a low voltage ("true") when both XA<0> and XA<1> are at high voltages (also "true"). Thus, the signal is given an .L polarity. If an AND gate had been used instead of NAND, the polarity would be .H. If a signal is not marked with a polarity indicator, it defaults to positive logic. To be absolutely clear, it is a good idea to mark all signals explicitly.

A signal with positive (.H) polarity is asserted at a high voltage level, and a signal with negative (.L) polarity is asserted at a low voltage level. A bubble on a logic symbol indicates that an input or output is inverted. An input with a bubble means that the input signal is to be asserted low. A bubbled output is asserted when its voltage is low. A bubbled input should almost always match a bubbled output or another signal that is specified as being asserted active low. Inputs and outputs without bubbles match .H signals or other bubbleless inputs and outputs.

Because it makes drawings so much easier to read, you should match bubbles wherever possible. Where they match, you can simply ignore polarity. For example, although Figure 2.64 and Figure 2.65 are equivalent, in Figure 2.65 it is much easier to see that five active high input signals are being ANDed together.

In a few cases, bubbles cannot be made to match. Usually these cases involve some form of inhibition. That is, when the signal is asserted, something is NOT happening.

Figure 2.66 shows an example where a clear pulse (ClearReg) is being controlled by another signal (Enable). The actual clear signal is active low and should be asserted only when both Enable and ClearReg are asserted. When the output of the NAND gate is high, the Clear signal is inhibited. Note the use of the positive logic form of the output signal polarity.

Since the gate's output is active low but the signal label is active high, we have a mismatch. It would be clearer if the gate output were labeled with the action that takes effect when the signal is asserted active low. Careful renaming of a signal can make the mismatch go away. In this case, you simply replace InhibitClear.H with EnableClear.L.

Crossovers and Connections All connections between wires must be marked with "blobs," as shown in Figure 2.67.

Be careful to make it crystal clear when signals cross without connection and when connections are made.

Hierarchical Documentation and Cross-References Large designs cannot fit on a single sheet of paper. They must be suitably distributed over many pages, and signals will cross page boundaries. Even if everything did fit on one sheet, it probably wouldn't be practical to draw wires for every connection: the sheet would turn into a rat's nest of lines. Thus, you need to make proper use of hierarchy and abstraction in your presentation of the design.

The first pages should contain a coarse block diagram showing the main group of components. Only signals that leave or enter one of these blocks should be shown. Subsequent pages will expand these blocks hierarchically into more and more details. Thus the same signal may appear in several disconnected places. It is important to keep track of where signals are used, making it easier to scan the drawings and to verify signal fan-outs.

You are expected to observe several conventions in order to keep track of signal usage. All inputs to a sheet should enter at the top or left edge of the sheet; all outputs from the sheet should terminate at the -bottom or right edge. If a signal is both an input and an output, you may take your pick.

Each page of your project should be named in some conspicuous place and should also be numbered. Signals that leave a page should carry a unique label and an indication of other pages on which they can be found entering. Correspondingly, all entering signals should carry the proper name label and an indication of the page from which they come. Ideally, if each page corresponds to some block in a previous page, then that previous page is a block diagram that shows all the interconnections between the blocks. The inputs and outputs to any block should correspond to all the entering and exiting signals on the detailed page and should carry the same signal names.

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