Registers and Counters

Storage Registers

A register is a group of storage elements read or written as a unit. The simplest way to construct a register is by grouping together as many D flip-flops as you need to obtain your desired bit width. Figure 7.1 shows a four-input register built by wiring together the clocks of four flip-flops.
The individual flip-flops have active low reset (R) and set (S) inputs. Since they affect the outputs independently of the clock, they are asynchronous. On the other hand, the D data inputs are synchronous. They are sampled only in conjunction with clocking events.
Figure 7.1 gives the implementation of a TTL 74171 "Quadruple D-type Flip-flop with Clear" register component, and Figure 7.2 gives its schematic shape.
The bubble notation shows which inputs and outputs are active low.
Circuits such as the one in Figure 7.1 are at the heart of almost all packaged registers. However, there are many variations on the basic theme, usually involving additional control signals for the inputs and outputs. One extension provides a load signal. The register's internal logic holds the current state on each clock as long as a load is not asserted. When a load is asserted, the new inputs are gated to the internal inputs of the flip-flops. These replace the current state when the clock edge arrives.

Another extension allows the register's outputs to be tri-state or open collector. In this way multiple registers can share common output wires. External logic selectively enables a single register to place its outputs on the shared wires.

As a concrete example, consider the TTL 74377 "Octal D-type Flip-flops with Enable" component. It is an eight-element register constructed from positive edge-triggered D flip-flops (see Figure 7.3(a)). It provides an active low input enable signal. When the load signal is low and the positive edge of the clock arrives, the flip-flops receive new data. Otherwise the current contents of the storage elements are held despite the clock transitions.

The TTL 74374 "Octal D-type Flip-flops with Tri-state Outputs" component contains an additional active low output enable signal (see Figure 7.3(b)). When this signal is driven low, the contents of the register are visible at the outputs. Otherwise, the outputs are tri-state.

Register Files If registers group multiple storage elements into a unit, then register files extend the grouping to multiple registers. Each register in the register file is called a word and is identified by a unique index or address.

The component contains its own internal decoders. In conjunction with an externally specified address, the decoders select a specific register file word to be written. On a read, the selected word is multiplexed to the outputs.
An example is the TTL 74670 "4-by-4 Register File with Tri-State Outputs," whose schematic shape is shown in Figure 7.4.
The device contains 16 D flip-flops organized into four words of four flip-flops each. The RB, RA and WB, WA inputs are driven with 2-bit binary encodings of one of four registers to be read or written, respectively.
The read enable () and write enable () inputs are active low. Because of the independent enable signals, it is possible to read and write this register file at the same time (presumably to different register words).

Interestingly, this device has no distinguished clock signal. It uses the signal and the write address bits to generate the clock inputs to the internal flip-flops. Because the component lacks an explicit clock, it should be used with great care. The write address lines must be stable before the signal arrives, otherwise the wrong word might be written. Any glitches on the signal could also lead to unwanted writes.

Random-Access Memories Registers are convenient for holding small amounts of information, usually in the range of 4 to 16 bits. However, many digital systems require substantially more storage elements than this. Random-access memory, or RAM, offers a solution. By using very transistor-efficient methods for implementing storage elements, RAM generalizes the register file concept to make many more words available in a single integrated circuit package. A small RAM might hold 256 four-bit words (1024 storage elements), a state-of-the-art device contains over 4 million storage elements, and 16-million-bit devices are on the way. Very fast but small-capacity RAMs are just as difficult to design as the very large but much slower memories. We cover RAMs in more detail in Section 7.6.

7.1.2 Shift Registers

Registers can be used for other applications besides simply storing bits. They are often used to circulate, or shift, values among the storage elements. In this subsection, we concentrate on register components that shift as well as store. These are called shift registers. Figure 7.5 shows the logic of a simple right-shifting circular shift register constructed from master/slave flip-flops. Data moves from left to right. On every shift pulse, the contents of a given flip-flop are replaced by the contents of the flip-flop to its left. The leftmost device receives its inputs from the rightmost. Because flip-flop propagation times far exceed hold times, the values are passed correctly from one stage to the next (we discussed cascaded flip-flops in Section 6.2.1).
The step-by-step operation of the shift register is shown graphically in Figure 7.6, for an initial configuration of Q1 = 1, Q2 = 0, Q3 = 0, Q4 = 0 followed by three shift pulses.
The values move from the left to the right and wrap around from right to left. We also show this in the timing diagram of Figure 7.7.

Variations: Parallel Versus Serial Inputs and Outputs Although the circuit of Figure 7.5 provides a primitive ability to shift, we have no way to load the shift register with an initial value! Most shift registers contain additional logic to load the internal flip-flops from external inputs. The two major ways to do this are through serial or parallel data inputs.

The serial input approach is the simpler of the two. Instead of having a feedback path between the rightmost and leftmost flip-flops, as in Figure 7.5, a shift register with serial inputs has an external connection to the leftmost flip-flop. The register is loaded by successively providing new values at the serial input, in conjunction with the shift pulse. Previously provided inputs shift through the elements of the register.

A shift register with parallel inputs contains multiplexing logic at the input to each internal flip-flop. The flip-flop receives a new value from its left neighbor when the shift register is in shift mode or from an external input when the register is in load mode.

A similar variation distinguishes between parallel and serial outputs. Parallel outputs mean that the outputs of the internal flip-flops are visible at the pins of the register's IC package. With serial outputs, only the value of the last element is visible outside the register, such as Q4 in Figure 7.5. The primary motivation for serial outputs is to reduce the number of output connections, since the flip-flop outputs are always available inside the shift register.
Example Universal Shift Register
To illustrate these concepts, let's consider the 74194 "4-Bit Bidirectional Universal Shift Register" TTL component.
Figure 7.8 shows its schematic shape and function table. This device can operate in four distinct modes, determined by the values at the control inputs S1 and S0: hold data (S1, S0 = 00), shift right QA toward QD (S1, S0 = 01), shift left QD toward QA (S1, S0 = 10), and parallel load from the A, B, C, D inputs (S1, S0 = 11). In addition, the register has an active low (asynchronous) reset signal CLR and two serial shift inputs LSI and RSI.
The parallel load takes place when S1 and S0 are both high and a rising edge arrives at the clock input. At the same time, the value at input A replaces the contents of the QA flip-flop, B replaces QB, and so on. This is called a synchronous load because it takes place in response to a clock event.

S1 low and S0 high indicate a right shift. On the rising edge of the clock, the value on the RSI input replaces QA, QA replaces QB, QB replaces QC, and QC replaces QD. The old value at QD is lost. We can construct a right circular shifter by wiring the QD output to the RSI input.

S1 high and S0 low specify a left shift. In this case, LSI replaces QD, QD replaces QC, QC replaces QB, and QB replaces QA, all on the rising edge of the clock. We can construct a left circular shifter by wiring QA to LSI.

S1 and S0 both low tell the shift register to hold its state. The outputs do not change even though the clock signal undergoes a low-to-high transition.

Sample Shifter Application Consider the problem of communicating between a terminal and a computer over phone lines. The terminal expects its data to appear in a byte-wide parallel form, but the data must be sent over the line in bit-serial form. Shift registers play a key role in such communication systems because they can convert between parallel and serial formats. We design the hardware to load the data from the computer in parallel and shift it out serially over the communications link. On the return trip, serial data from the terminal is captured by the shift register, bit by bit, and presented to the computer via the shift register's parallel outputs.
A partial implementation of this subsystem is shown in Figure 7.9.
On the sender side, we load 8 bits of parallel data into the cascaded shift -register by setting S1, S0 to 1, 1. The sender and receiver then enter their shift-left mode when S1, S0 are set to 0, 1. We do this for eight clock cycles, transmitting D0 through D7, 1 bit at a time. Once all 8 bits have been sent, we can place the receiver in its hold mode by setting S1, S0 to 0, 0.

7.1.3 Counters

Counters are sequential logic circuits that proceed through a well-defined sequence of states. We study them in more detail in this subsection.

Up-Counters and Down-Counters An up-counter proceeds from a value to the next larger value in the sequence in response to a count pulse. The counter outputs are identical to the state of the internal flip-flops. Once the largest possible value has been reached, the sequence restarts with the smallest value. For example, a 3-bit binary up-counter begins in state 000; goes through the sequence 001, 010, 011, 100, 101, 110, 111; and returns to 000, 001, and so on.

As you might expect, a down-counter operates similarly except that it sequences from large values to smaller values. The counter wraps from the smallest possible value back to the largest value in the sequence.

Binary, Decade, Gray Code Counters Although we have been describing binary counters, a counter can be designed to advance through any periodic sequence. Popular alternatives to binary counters are decade counters. These sequence through the BCD digits: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001.

In some applications, to avoid circuit hazards, it is important that only a single bit of the counter changes at a time. The binary and decade counters do not exhibit this property. However, a Gray code counter does. A 4-bit Gray code up-counter would sequence through the states 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000 and repeat.

Ring Counters The shift register implementation of Figure 7.5 can also be used as a kind of primitive counter, a ring counter. The shifter sequences through the states 1000, 0100, 0010, 0001 and then repeats. The ring counter uses minimal hardware for its implementation, but it does not encode its states as efficiently as the counters we have just described. The four-element ring counter sequences through only 4 states, compared with the 16 states of the four-element binary counter.

A Johnson counter (also known as a Mobius counter) requires no more hardware than the basic ring counter but can represent twice as many states. The idea is to "twist around" the feedback outputs of the rightmost flip-flop to yield the shifter/ring counter. This has the effect of complementing the bit shifted out to the right before it is reinserted into the shifter from the left. We show an implementation of the 4-bit Johnson counter with master/slave J-K flip-flops in Figure 7.10.
We use the asynchronous set and reset inputs to force the flip-flops into the initial state 1000 when reset is asserted.
Figure 7.11 shows the timing diagram. The counter sequences through the states 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 and repeats. It happens that this sequence satisfies the same property as the Gray code: only a single bit changes its value from one state to the next.
Applications and Example Catalog Counter Counters are used in digital systems to count events and find many applications in tracking the passage of time. See Exercise 7.23 at the end of this chapter for some design problems.

Let's examine a counter component from the TTL catalog. Figure 7.12 shows the schematic shape of the TTL 74163 synchronous 4-bit counter. The component has four data inputs, four data outputs, four control inputs (P, T, , ), one control output (RCO), and the clock.

When the signal is asserted, the data inputs replace the contents of the counter's internal flip-flops. Similarly, when is asserted, all the flip-flops are reset to zero. These operations are synchronous. Although the load or clear signal must be asserted before the clock edge, the actual operation occurs on the positive transition of the clock. Contrast this with asynchronous operation, in which the load or clear takes place as soon as the appropriate control signal is asserted. We will say more about synchronous versus asynchronous counter operation in Section 7.5.

The P and T inputs cause the counter to advance to the next state in the binary sequence when both are asserted. Again, the count operation takes place when the clock undergoes a low-to-high transition. RCO is a ripple carry output that is asserted after the same rising clock edge that advances the counter to its largest value, 1111. This signal can be used as a count enable signal to a second cascaded counter (see Section 7.5.1).
The timing waveform of Figure 7.13 illustrates the interaction of these signals.
When the clear signal is asserted, the counter's outputs are set to 0 on the next rising clock edge. When load is asserted, the counter is preset to 1100, the data on the parallel load inputs. When the count enable inputs, P and T, are enabled simultaneously, the counter counts up on each subsequent rising clock edge. As soon as the counter's output reaches 15, the RCO output is asserted. When either of P or T becomes unasserted, the counter stops counting and holds its current value through subsequent rising edges of the clock.