4.1. Register Transfer Language and Hardware Description Language
System design uses a modular approach with components at the
level of registers, multiplexers, decoders, adders. Gate level
design is generally limited to designing the components, although
some individual gates may be used to connect larger
components.
Microoperations are the basic operations that can be performed by a system on data stored in registers. Each microoperation describes a simple operation performed on data in one or more registers.
Microoperations are the basic operations that can be performed by a system on data stored in registers. Each microoperation describes a simple operation performed on data in one or more registers.
Microoperations can be expressed in terms of a
Register Transfer Language (RTL).
Trying to describe the design in words is pure folly.
A register transfer language is a type of Hardware Description Language (HDL)
Since a CPU is a synchronous sequential circuit, microoperations occur at regular intervals when triggered by the clock pulse. All sequential circuits in the CPU are generally driven by the same clock in order to remain in sync.
For each clock cycle, zero or more microoperations occur in the CPU. There is no limit to how many microoperations can occur at once, provided that no two microoperations require the same circuit to do different things. Hence, hardware design is somewhat like parallel programming.
A register transfer language is a type of Hardware Description Language (HDL)
Since a CPU is a synchronous sequential circuit, microoperations occur at regular intervals when triggered by the clock pulse. All sequential circuits in the CPU are generally driven by the same clock in order to remain in sync.
For each clock cycle, zero or more microoperations occur in the CPU. There is no limit to how many microoperations can occur at once, provided that no two microoperations require the same circuit to do different things. Hence, hardware design is somewhat like parallel programming.
A CPU architecture (as you learned in CS 315) is defined
by the instruction set (machine language). But how is each
of the machine instructions defined?
A transfer statement implies availability of inputs on
the destination register, outputs on the source register(s),
and parallel load capability.
Figure 4-2
Table 4-1 (Basic symbols for register transfer)
- Set of registers and their functions (capabilities)
- Sequence of microoperations performed on the data stored in registers (instructions based on microinstructions)
- Control signals that initiate the sequence
4.2. Register Transfer
- Register names use capital letters possibly followed by numbers, e.g. PC, R0, R1, ...
- Individual bits are numbered according to the power of two when they contain an unsigned binary integer. I.e. the rightmost bit is bit 0, next is bit 1, etc. Bits are numbered this way regardless of whether the register contains an unsigned binary integer, because it's an easy convention.
- Registers drawn as a box with the name inside. Bit numbers are written above.
- 16-bit registers may be divided into low and high bytes in both diagrams and in writing, e.g. PC(8-15) = PC(H), PC(0-7) = PC(L).
-
A control function is a Boolean condition upon which a transfer
depends. For example:
The same conditional transfer can be written as:
P: R2 ← R1
The control function is P and the microoperation is R2 ← R1. Every register transfer consists of a control function and a microoperation.
Figure 4-2
+----------+ P --------> |ld R2 |<--------- CK +----------+ ^^^^^^^^ |||||||| |||||||| +----------+ | R1 | +----------+If the registers are leading-edge triggered, where does the transfer occur?
CK _-_-_-_-_-_-_-_-_-_-_-_- P _____--_______------____Multiple microoperations occurring at the same time are separated by commas:
T: R2 ← R1, R1 ← R2Note: If newly loaded contents propagate to outputs while LD is enabled and the clock trigger is still active, what will happen? ( This is why we use edge-triggered sequential circuits. )
Table 4-1 (Basic symbols for register transfer)
4.3. Bus and Memory Transfers
If a computer has 16 registers, each holding 32 bits, how many
wires are needed to connect every register to every other?
(162) For a large number of wide
registers, the wires could end up taking most of the space in
the circuit.
A BUS is a single shared set of wires connecting all registers.
Figure 4-3, bus system for 4 registers using multiplexers.
Bus, 4 8-bit registers connected for input and output. Use decoder/demux to drive load input on registers. Wire one MUX. Clock speed is limited by the propagation delay through the MUX and wires.
Only one register's contents can be on the bus for a given clock cycle. Which of the following are legal?
Book error: No R1 in the diagram.
3-state gates
3-state buffers can be used instead of multiplexers. A 3-state buffer is a combinational circuit that acts like a simple switch: It either passes the input signal to the output (C=1), or blocks the electrical current (C=0). The latter case is called high impedance state.
A BUS is a single shared set of wires connecting all registers.
Figure 4-3, bus system for 4 registers using multiplexers.
Bus, 4 8-bit registers connected for input and output. Use decoder/demux to drive load input on registers. Wire one MUX. Clock speed is limited by the propagation delay through the MUX and wires.
Only one register's contents can be on the bus for a given clock cycle. Which of the following are legal?
- A ← B, C ← D
- A ← C, D ← C
- B ← D, B ← A
BUS ← C, A ← BUSCan be written as:
A ← CMultiplexers must be driven to select register C t time units before the clock pulse that loads A, where t is the propagation delay of the multiplexers.
3-state gates
3-state buffers can be used instead of multiplexers. A 3-state buffer is a combinational circuit that acts like a simple switch: It either passes the input signal to the output (C=1), or blocks the electrical current (C=0). The latter case is called high impedance state.
I ------|>-------- O | C -------+3-state buffers can be used to connect or disconnect register outputs to/from the bus. A single decoder can control a large number of 3-state buffers. The outputs of the 3-state buffers can be tied directly together, provided that the circuit guarantees that all but one will be in high-impedance state at any given time. Using a decoder to control them guarantees this.
The internal bus connects only registers within the CPU, so
how do we get data to and from memory?
The address register (AR) is used to select a memory address, and the data register (DR) is used to send and receive data. Both these registers are connected to the internal bus. DR is a bridge between the internal BUS and the memory data BUS.
Memory can also be connected directly to the internal BUS in theory.
Diagram showing connections to memory unit.
Increment and decrement can be done with combinational incrementers and decrementers, counter registers, or by adding a 1. ( Where does the 1 come from? )
Multiply and divide are not often implemented as microoperations due to the amount of time they require. They are usually implemented as a multi-clock-cycle routine of shifts and adds.
The address register (AR) is used to select a memory address, and the data register (DR) is used to send and receive data. Both these registers are connected to the internal bus. DR is a bridge between the internal BUS and the memory data BUS.
Memory can also be connected directly to the internal BUS in theory.
Diagram showing connections to memory unit.
M[AR] ← DR DR ← M[AR]Hence, accessing memory outside the CPU requires at least two clock cycles. First we load AR with the desired memory address, and then transfer to or from DR. In most typical computer systems, memory transfers take many clock cycles, known as wait states.
4.4. Arithmetic Microoperations
- Register Transfer
- Arithmetic (Addition, subtraction, ...) Data is numeric, and bits with a word are interdependent.
- Logic (AND, OR, ...) Data is not numeric, and bits are independent of each other. The same logical operation is applied to each bit in a word in parallel.
- Shift. Data may or may not be numeric. All bits are moved the same number of positions left or right.
Table 4.2.
| Example | Description |
|---|---|
| R3 ← R1 + R2 | Addition |
| R3 ← R1 - R2 (R1 + R2' + 1) | Subtraction |
| R2 ← R2' | Complement (really a logic operation) |
| R2 ← -R2 (R2' + 1) | Negation |
| R1 ← R1 + 1 | Increment |
| R1 ← R1 - 1 | Decrement |
Increment and decrement can be done with combinational incrementers and decrementers, counter registers, or by adding a 1. ( Where does the 1 come from? )
Multiply and divide are not often implemented as microoperations due to the amount of time they require. They are usually implemented as a multi-clock-cycle routine of shifts and adds.
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